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Electronic Components and Technology Conference
| Venue: | Sheraton San Diego Hotel & Marina | ||
| Country: | San Diego, United States Of America | ||
| Start Date: | End Date: | ||
| Categories: | Electronics & Electricals | ||
CONFERENCE DESCRIPTION
62nd Electronic Components and Technology Conference (ECTC) will a premier conference sponsored by the IEEE-CPMT Society to cover the field of optoelectronics, interconnections, reliability and simulation. The conference will provide plenary session on Power Efficiency Challenges and Solutions: From Outer Space to Inside the Human Body and panel discussion to address selected topics The symposium will also provide Professional Development Courses on Achieving high Reliability of Lead-Free Soldering Materials Consideration, Wafer Level-Chip Scale Packaging (WLCSP) and Electronics, Energy, and the Environment. Electronic Components and Technology Conference (ECTC) discuss about Technology Advances in 3D-TSV Integration and Packaging of Micro-Nano Systems, Flip Chip Fabrication and Interconnection and Packaging of High Brightness (HB) LED for Solid State Lighting.
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Conference Programme
Day 1 Programme, 30-May-2012
Summary : It will give cover Chip-to-Wafer (C2W) 3D Integration with Well-Controlled Template-Alignment and Wafer-Level Bonding, Embedded and Wafer Level Packaging and Minor Alloying Effects of Ni or Zn on Microstructure and Microhardness of Pb-free Solders and poster sessions
08:00 AM - 08:25 AM
Chip-to-Wafer (C2W) 3D Integration with Well-Controlled Template-Alignment and Wafer-Level Bonding
08:25 AM - 08:50 AM
Fluxless Bonding for Fine-pitch and Low-volume Solder 3-D Interconnection
08:50 AM - 09:15 AM
Development of Fluxless Chip-On- Wafer Bonding Process for 3D Chip Stacking with 30um Pitch Lead-free Solder Micro Bump Interconnection and Reliability Characterizatio
10:00 AM - 10:25 AM
Thermal Reliability of Fine Pitch Cu-Cu Bonding with Self Assembled Monolayer (SAM) Passivation for Wafer-on-Wafer 3D-Stacking
10:25 AM - 10:50 AM
High Density 20μm Pitch CuSn Microbump Process for high-end 3D Applications
10:50 AM - 11:15 AM
Homo/Heterogeneous Bonding of Cu, SiO2, and Polyimide by Low Temperature Vapor- Assisted Surface Activation Method
11:15 AM - 11:40 AM
High Resolution Acoustical Imaging of High-Density-Interconnects for 3D-Integration
13:30 PM - 13:55 PM
3D Chip Stacking with 50 micron Pitch Lead-free Micro-C4 Interconnections
13:55 PM - 14:20 PM
Development of 3D TSV Super Thin PoP for Mobile Applications
14:20 PM - 14:45 PM
Design, Simulation and Process Optimization of AuInSn Low Temperature TLP Bonding for 3D IC Stacking
15:30 PM - 15:55 PM
Through Silicon Via (TSV) Interposers and Interconnects for High-Performance Applications
15:55 PM - 16:20 PM
A Study on Wafer Level Molding for Realizing 3-D Integration
16:20 PM - 16:45 PM
Through Silicon Via Stacking & Numerical Characterization for Multi-Die Interconnections using Full Array & Very Fine Pitch Micro C4 Bumps
16:45 PM - 17:10 PM
Process Integration and Reliability Test for 3D Chip Stacking with Thin Wafer Handling Technology
Organizer:
Tel:+(1)-(212)-4197900
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